Manufacture of various semiconductor devices such as memory devices, logic devices, and microprocessors has the common goal of miniaturization. As feature sizes decrease, electrical operation of semiconductor devices, for example transistor functionality, becomes more difficult. One contributing factor to this difficulty is known as the “short channel effect” in which the length of the transistor channel becomes excessively small due to miniaturization. This may result in the transistor activating even though a threshold voltage (Vt) has not been applied to the gate. Another obstacle to miniaturization is resistance of the gate, which increases with decreasing cross sectional area.
One type of device which has been developed to overcome gate resistance and the short channel effect of a conventional transistor is referred to as a “recessed access device” or “RAD” transistor. Devices of this type comprise a channel which is longer than conventional devices, but requires only a similar horizontal space. One type of RAD transistor comprises a transistor gate (word line) which is partially formed within a trench in a semiconductor wafer. The channel region is formed along the entire surface of the trench which, in effect, provides a longer channel and increases cross sectional area of the gate without increasing the lateral space required by the transistor.
A conventional method to form an n-channel metal oxide semiconductor (NMOS) RAD transistor is depicted in FIGS. 1-6. FIG. 1 depicts a semiconductor wafer 10, which may be doped predominantly with p-type dopants, and a pad dielectric (pad oxide) 14 formed on a major surface of the semiconductor wafer which protects the wafer 10 from a patterned mask 16, which is typically photoresist. An anisotropic etch is performed on the FIG. 1 structure to form the trench 20 within the wafer 10 as depicted in FIG. 2. Element 22 denotes the future transistor channel. It should be noted that other process flows for forming the depicted structures or functionally similar structures are possible.
After forming the FIG. 2 structure, the photoresist 16 and the pad oxide 14 are removed and a transistor gate oxide material 30 is formed over the exposed semiconductor wafer 10. Next, various blanket transistor gate materials are formed as depicted in FIG. 3, including gate material 32, a silicide material 34, and a nitride capping material 36. Gate material 32 may comprise any or all of doped and undoped polysilicon, titanium nitride, tantalum nitride, and ruthenium. A patterned photoresist material 38 is then formed which may be used to define the transistor gate. The FIG. 3 structure is anisotropically etched towards the gate oxide 30, the photoresist material 38 is removed, and a source-drain implant is performed to provide cell 40 and digit 42 (i.e. source and drain) regions and to result in the formation of the transistor gate of FIG. 4, which comprises materials 32, 34, and 36. A blanket spacer material 50, for example silicon nitride, is formed over the structure of FIG. 4 to result in the FIG. 5 structure, and a spacer etch is then performed to form insulative spacers 60 around the transistor gate as depicted in FIG. 6. The formation of the insulative spacers 60 also completes the transistor gate structure. In the structure of FIG. 6, implanted regions 40, 42 represent transistor source/drain regions, although other impurity implants, such as a halo implant, may be performed during fabrication.
Another type of RAD device is referred to as a “sphere-shaped recess channel array transistor” (S-RCAT). This device is depicted in FIG. 7, and is described in “S-RCAT (Sphere-shaped Recess Channel Array Transistor) Technology for 70 nm DRAM features size and beyond”, J. Y. Kim et al., 2005 Symposium on VLSI Technology Digest of Technical Papers, June 2005, pp. 34-35. The gate 32 comprises a neck 70 and a rounded portion (ball or sphere) 72 formed within the wafer 10. With this device using a 70 nm design rule, the neck 70 is about 770 Å wide and about 660 Å in height, and the rounded portion 72 is about 1,100 Å in diameter. Doped region 40 extends from the upper major surface of the wafer down to about 1/2 the height of rounded portion 72, and is about 1,200 Å below the surface of the wafer. The interface between n-type doped region 40 and the p-type wafer 10 thus defines the metallurgical junction, while the transistor channel 22 is defined by the lower half of the circumference of the rounded portion, which would be about 1,725 Å. The width of the semiconductor wafer material between adjacent balls is 300 Å.
The configuration of the S-RCAT gate has an increased cross sectional area, forms a longer channel, and further reduces short channel effects over a conventional transistor device. However, with the n-type doping of the cell extending from the surface of wafer 10 towards the middle of the rounded portion 72, the metallurgical junction is about 1,200 Å deep. This increased depth over other RAD devices may increase gate induced drain leakage (GIDL) current due to a large overlap of the active area 40 and the gate 32. The RAD device of FIG. 6 avoids this GIDL as the vertical overlap between gate 32 and active area 40 is small, due to the shallow metallurgical junction, depicted as the bottom line of doped region 40.
A method for forming semiconductor device comprising a RAD transistor which has an increase surface area, increased channel length, and decreased overlap between the junction area and the gate than previous devices would be desirable.
It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which can be determined by one of skill in the art by examination of the information herein.